Starting kernel ... [ 0.000000] Linux version 4.14.78 (arny@depc0045) (gcc version 7.3.0 (OpenWrt GCC 7.3.0 r0+8403-fa8e9a8889)) #0 SMP Sun Dec 2 16:35:45 2018 ... [ 2.258362] samsung_nand_decode_id: ID is len=6, EC DC 10 95 54 EC EC DC <-------------------- Info [ 2.263636] samsung_nand_decode_id: original chip->ecc_step_ds=0, chip->ecc_strength_ds=0 [ 2.271801] samsung_nand_decode_id: changed chip->ecc_step_ds=512, chip->ecc_strength_ds=1 [ 2.280157] samsung_nand_decode_id: id.data[1] is 0xDC, allowing subpage writes [ 2.287471] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xdc [ 2.293822] nand: Samsung NAND 512MiB 3,3V 8-bit [ 2.298439] nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64 [ 2.306695] Bad block table found at page 262080, version 0x01 [ 2.312642] Bad block table found at page 262016, version 0x01 [ 2.317960] nand_read_bbt: bad block at 0x000004200000 [ 2.322955] nand_read_bbt: bad block at 0x0000142c0000 [ 2.328249] 16 fixed-partitions partitions found on MTD device 14000000.nand [ 2.335041] Creating 16 MTD partitions on "14000000.nand": [ 2.340553] 0x000000000000-0x000000040000 : "uboot" [ 2.347168] 0x000000040000-0x000003c40000 : "rootfs1" [ 2.353317] 0x000003c40000-0x000004140000 : "kernel" [ 2.358704] 0x000004140000-0x000004240000 : "tmp1" [ 2.363836] 0x000004240000-0x000004440000 : "tmp2" [ 2.368934] 0x000004440000-0x000004540000 : "sysconfig" [ 2.374535] 0x000004540000-0x000004640000 : "ubootconfig" [ 2.380245] 0x000004640000-0x000004700000 : "fwdiag" [ 2.385479] 0x000004700000-0x000004a00000 : "lcdimage" [ 2.391102] 0x000004a00000-0x000004b00000 : "mfgconfig" [ 2.396641] 0x000004b00000-0x000004c00000 : "sipdata" [ 2.401989] 0x000004c00000-0x000008c00000 : "voice" [ 2.408113] 0x000008c00000-0x00001be00000 : "ubi" [ 2.417214] 0x00001be00000-0x00001fa00000 : "rootfs2" [ 2.423419] 0x00001fa00000-0x00001ff00000 : "kernel2" [ 2.428804] 0x00001ff00000-0x000020000000 : "mystery" [ 2.437287] rtl8367b rtl8367b: cannot find mdio bus from bus handle, try again later ... root@OpenWrt:~# cd /sys/class/mtd/mtd12 root@OpenWrt:/sys/devices/platform/1f400000.fpi/1f400000.fpi:localbus@0/14000000.nand/mtd/mtd12# grep "" * bad_blocks:1 bbt_blocks:0 bitflip_threshold:1 corrected_bits:0 dev:90:24 ecc_failures:0 I later modified nand_samsung.c and VGV952CJW33-E-IR.dts and removed certain lines... ecc_step_size:256 seems not to be affected by "chip->ecc_step_ds=512" in nand_samsung.c or by "nand-ecc-step-size = <256>" in dts ecc_strength:1 seems not to be affected by "chip->ecc_strength_ds=1" in nand_samsung.c or by "nand-ecc-strength = <3>" in dts erasesize:131072 flags:0x400 name:ubi numeraseregions:0 offset:146800640 oobsize:64 size:320864256 subpagesize:512 type:nand uevent:MAJOR=90 uevent:MINOR=24 uevent:DEVNAME=mtd12 uevent:DEVTYPE=mtd uevent:OF_NAME=partition uevent:OF_FULLNAME=/fpi@10000000/localbus@0/nand@0/partitions/partition@8C00000 uevent:OF_COMPATIBLE_N=0 writesize:2048 root@OpenWrt:/sys/devices/platform/1f400000.fpi/1f400000.fpi:localbus@0/14000000.nand/mtd/mtd12# ================= from nand_samsung.c static void samsung_nand_decode_id(struct nand_chip *chip) { struct mtd_info *mtd = nand_to_mtd(chip); u8 *d = chip->id.data; printk("samsung_nand_decode_id: ID is len=%d, %02X %02X %02X %02X %02X %02X %02X %02X\n", chip->id.len, d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7]); /* New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) */ if (chip->id.len == 6 && !nand_is_slc(chip) && ... nand_decode_ext_id(chip); if (nand_is_slc(chip)) { switch (chip->id.data[1]) { /* K9F4G08U0D-S[I|C]B0(T00) */ case 0xDC: printk("samsung_nand_decode_id: original chip->ecc_step_ds=%d, chip->ecc_strength_ds=%d\n", chip->ecc_step_ds, chip->ecc_strength_ds); chip->ecc_step_ds = 512; chip->ecc_strength_ds = 1; printk("samsung_nand_decode_id: changed chip->ecc_step_ds=%d, chip->ecc_strength_ds=%d\n", chip->ecc_step_ds, chip->ecc_strength_ds); if (chip->id.len > 4 && (chip->id.data[4] & GENMASK(1, 0)) == 0x1){ chip->options |= NAND_NO_SUBPAGE_WRITE; } else { printk("samsung_nand_decode_id: id.data[1] is 0x%02X, allowing subpage writes\n", d[1]); } break; /* K9F1G08U0E 21nm chips do not support subpage write */ ...